In many high performance applications, precise comparisons of two (or more signals) is conducted. As a results of process variation (during manufacturing) as well as other factors, there can be transistor mismatches that result in an input offset or offset voltage. In conventional systems (such as system 100) of FIG. 1, compensation for offset was accomplished by providing multiple, substantially identical comparators 102-1 to 102-N in parallel with one another. Based on testing of these comparators 102-1 to 102-N, the “best” comparator (of comparators 102-1 to 102-N) can be selected by application of a select signal to multiplexer or mux 104. This configuration, however, can waste a significant amount of area because the majority of comparators 102-1 to 102-N are unused.
To illustrate this point, a plot showing 10 simulation trials for 1000 comparators in a 7 comparator array (which, for example, can be used with a 3-bit flash comparator) with the worst-case offset for each trial being recorded can be in FIG. 2. For these trials, 7 comparators were chosen from sets having 0 (7pick7) to 5 (12pick7) redundant comparators. The redundancy does indeed help reduce the worst-case offset, but a point of diminishing returns is quickly reached, as the set with 4 redundant comparators (11pick7) has a similar worst-case offset to the set with 5 redundant comparators (12pick7). Additionally, with 5 redundant comparators, the extra area overhead is 71%. Thus, there is a need for an improved comparator having a reduced offset.
Another example of a conventional circuit is U.S. Pat. No. 7,474,129.